Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects
Alimin, A.F.M.; Radzi, A.A.M.; Sazali, N.A.F.; Hatta, S.F.W.M.; Soin, N.; Hussin, H.
Journal of Electronic Materials 46(10): 5942-5949
2017
ISSN/ISBN: 0361-5235 DOI: 10.1007/s11664-017-5575-9
Accession: 084786183
Full-Text Article emailed within 0-6 h
Payments are secure & encrypted
References
Lee, D.; Huang, T.; Lin, H.C.; Chiang, W.; Huang, G.; Wang, T. 2004: Effects of Process and Gate Doping Species on Negative-Bias-Temperature Instability of p-Channel MOSFETs Journal of the Electrochemical Society 151(2): G144-G148Zhou, A.; Liu, J.; Zheng, K.; Ju, J.; Zhang, J.; Gan, Z.; Ho, H.; Ning, X. 2019: Fluorine IMP Effect on Negative Bias Temperature Instability and Process Induced Defects ECS Transactions 27(1): 67-72
Yun, Y.; Kim, G.; Seo, J.; Son, D.; Kang, B. 2018: Method to extract parameters of power law for nano-scale Si ON p MOSFETs under negative bias temperature instability Microelectronics Reliability 88-90: 191-195
Sim, P.C.; Koo, S.S.; Pal, D.K. 2019: High Voltage Device Negative Bias Temperature Instability Improvement with Different Process Conditions ECS Transactions 34(1): 967-972
Houssa, M.; Aoulaiche, M.; De Gendt, S.; Groeseneken, G.; Heyns, M.M. 2007: Negative bias temperature instabilities in HfSiO(N)-based MOSFETs : Electrical characterization and modeling : Modelling the negative bias temperature instability Microelectronics and Reliability 47(6): 880-889
Jang, T.S.; Ha, M.H.; Yoo, K.D.; Kang, B.K. 2006: Effect of plasma process-induced damage on bias temperature instability of MOSFETs Microelectronic Engineering 83(3): 415-422
Lee, S.; Kim, C.; Kim, H.; Kim, G.; Seo, J.; Son, D.; Kang, B. 2013: Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate p MOSFETs Microelectronics Reliability 53(9-11): 1351-1354
Zhu, B.; Suehle, J.S.; Chen, Y.; Bemstein, J.B. 2002: Negative bias temperature instability of deep sub-micron p-MOSFETs under pulsed bias stress IEEE International Integrated Reliability Workshop Final Report 2002-January: 125-129
Gong, X.; Su, S.; Liu, B.; Wang, L.; Wang, W.; Yang, Y.; Cheng, R.; Kong, E.; Cheng, B.; Han, G.; Yeo, Y. 2013: Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and Hf O2 High-k and Ta N Metal Gate ECS Transactions 50(9): 949-956
Scarpa, A.; Ward, D.; Dubois, J.; Van Marwijk, L.; Gausepohl, S.; Campos, R.; Kwang Ye, S.I.M.; Cacciato, A.; Kho, R.; Bolt, M. 2006: Negative-bias temperature instability cure by process optimization Ieee Trans. Electron Devices 53(6): 1331-1339
Ho, S.; Chang, T.; Wu, C.; Lo, W.; Chen, C.; Tsai, J.; Chen, H.; Liu, G.; Tseng, T.; Cheng, O.; Huang, C.; Chen, D.; Sze, S.M. 2013: Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with Hfx Zr1−x O2and Hf O2/Metal Gate Stacks ECS Journal of Solid State Science and Technology 2(9): Q187-Q191
Ortiz Gonzalez, J.; Alatise, O.M.; Mawby, P.A. 2019: Novel method for evaluation of negative bias temperature instability of SIC MOSFETS Materials Science Forum 963 MSF: 749-752
Ho, W.; Park, S.; Kim, D.; Han, I.; Lee, H.; Kim, J.; Park, Y.; Kim, D. 2006: Novel Back End-of-Line Process Scheme for Improvement of Negative Bias Temperature Instability Lifetime Japanese Journal of Applied Physics 45(4A): 2455-2458
Liu, C.; Pan, T. 2007: Hot carrier and negative-bias temperature instability reliabilities of strained-Si MOSFETs IEEE Transactions on Electron Devices 54(7): 1799-1803
Guo, A.; del Alamo, J.A. 2017: Unified Mechanism for Positive- and Negative-Bias Temperature Instability in Ga N MOSFETs IEEE Transactions on Electron Devices 64(5): 2142-2147
Yang, J.B.; Chen, T.; Tan, S.S.; Ng, C.M.; Chan, L. 2019: Modeling and Characterization of Negative Bias Temperature Instability in p-Channel MOSFETs ECS Transactions 6(3): 283-299
Liu, C.H.; Pan, T.M. 2007: Hot carrier and negative-bias temperature instability reliabilities of strained-Si MOSFETs Ieee Trans. Electron Devices 54(7): 1799-1803
Yang, L.; Bai, Y.; Li, C.; Chen, H.; Tang, Y.; Hao, J.; Yang, C.; Tian, X.; Lu, J.; Liu, X. 2022: Bias Temperature Instability of 4H-SiC p- and n-Channel MOSFETs Induced by Negative Stress at 200 °c IEEE Transactions on Electron Devices 69(6): 3042-3046
Gonzalez, J.O.; Alatise, O. 2021: Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in Si C Power MOSFETs IEEE Transactions on Industry Applications 57(2): 1664-1676
Houssa, M.; Parthasarathy, C.; Espreux, N.; Revil, N.; Autran, J.L. 2003: Model for negative bias temperature instability in p-MOSFETs with ultrathin oxynitride layers J. Non-Cryst. Solids 322(1-3): 100-104